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I. Bayraktaroglu and A. Orailoglu,
“The construction of optimal deterministic partitionings in scan-based
BIST fault diagnosis: Mathematical foundations and cost-effective implementations”
submitted to IEEE Transactions on Computers
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I. Bayraktaroglu and A. Orailoglu,
“Concurrent test for digital linear systems” submitted to IEEE Transactions
on Computer Aided Design
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I. Bayraktaroglu and A. Orailoglu,
“Test volume and application time reduction through scan
chain concealment” to be presented in Design Automation Conference,
June 2001.
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I. Bayraktaroglu and A. Orailoglu,
“Rapid fault diagnosis through cost-effective deterministic partitioning
in scan-based BIST” to be published in IEEE Design & Test of Computers
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I. Bayraktaroglu and A. Orailoglu,
“Diagnosis for scan-based BIST: Reaching deep into the
signatures” In Design Automation and Test in Europe Conference,
March 2001.
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I. Bayraktaroglu and A. Orailoglu,
“Improved methods for fault diagnosis in scan-based BIST”
In Latin American Test Workshop, pages 169-172, February 2001.
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I. Bayraktaroglu and A. Orailoglu,
“Accumulation-based concurrent fault detection for linear
digital state variable systems” In Asian Test Symposium, pages
484-488, December 2000.
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I. Bayraktaroglu and A. Orailoglu,
“Deterministic partitioning techniques for fault diagnosis
in scan-based BIST” In International Test Conference, pages
273-282, October 2000.
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I. Bayraktaroglu and A. Orailoglu,
“Low cost concurrent test implementation for linear digital
systems” In European Test Workshop, pages 140-143, May 2000.
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I. Bayraktaroglu and A. Orailoglu, “Improved fault
diagnosis in scan-based BIST via superposition” In Design Automation Conference,
pages 55-58, June 2000.
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I. Bayraktaroglu and A. Orailoglu,
“Unifying methodologies for high fault coverage concurrent
and off-line test of digital filters” In IEEE International Symposium
on Circuits and Systems, pages 705-708, May 2000.
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I. Bayraktaroglu and A. Orailoglu,
“Cost effective digital filter design for concurrent
test” In International Conference on Acoustic, Speech and Signal
Processing, pages 3323-3326, June 2000.
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Y. Makris, I. Bayraktaroglu, and A. Orailoglu, “Invariance-based on-line test for RTL controller-datapath
circuits” In IEEE VLSI Test Symposium, pages 459-464, April
2000.
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S. Ozev, I. Bayraktaroglu, and A. Orailoglu,
“Test synthesis for mixed signal SOC paths” In Design
Automation and Test in Europe Conference, pages 128-133, March 2000.
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I. Bayraktaroglu and A. Orailoglu,
“Combined on-line/off-line test solutions for digital
filters” In IEEE International On-Line Testing Workshop, pages
34-38, July 1999.
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I. Bayraktaroglu and A. Orailoglu,
“Low-cost on-line test for digital filters” In IEEE
VLSI Test Symposium, pages 446-451, April 1999.
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I. Bayraktaroglu, S. Ogrenci, G. Dundar, S. Balkir,
and E. Alpaydin, “ANNSyS:
An analog neural network synthesis system” In Neural Networks,
vol.12(2), pages 325-338, March 1999.
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I. Bayraktaroglu, K. Udawatta, and A. Orailoglu,
“An examination of PRPG selection approaches for large,
industrial VLSI designs” In Asian Test Symposium, pages 440-444,
December 1998.
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I. Bayraktaroglu, S. Ogrenci, G. Dundar, S. Balkir,
and E. Alpaydin, “ANNSyS:
An analog neural network synthesis system” In International Conference
on Neural Networks, June 1997.
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I. Bayraktaroglu, S. Ogrenci, G. Dundar, S. Balkir,
and E. Alpaydin, “On-chip
training by software for analog neural networks using ANNSyS” In NASA
Symposium on VLSI, March 1997.
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I. Bayraktaroglu, S. Balkir, and G. Dundar,
“ANNSiS: A circuit level simulator for analog neural networks”
In Turkish Symposium on Artificial Intelligence and Neural Networks,
pages 305-310, June 1996.